Product brief

High-throughput device verification for EDA

With advanced system-on-a-chip (SoC) designs, verification is a growing challenge for chip design companies. Cadence Xcelium Parallel Logic Simulation on HPE Apollo 70 systems provides a cost-effective, high-performance alternative to existing solutions.
In electronic design automation (EDA), verification is about making sure that chip designs execute correctly and reliably. The process of taping out a design to create a photomask can cost millions of dollars, so designs need to be error-free before they are sent to a foundry. Regression testing involves running and rerunning up to millions of tests developed along with the design to ensure that it functions as expected throughout the SoC design project. As processor clock speeds plateau, engineers increasingly depend on fast, multithreaded simulation software, and high-throughput multicore server platforms to meet growing verification workload demands and time-to-market requirements.
Cadence Xcelium Parallel Logic Simulation is a new breed of third-generation simulator combining features of second-generation simulators (that run compiled code) with a new multithreaded engine that takes advantage of modern multicore systems such as the Arm-based HPE Apollo 70.